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1. abstract a methodology capable to digitally control and, in particular, properly turn-off one or two mosfets used as rectifiers in switched mode power supply (smps) isolated topologies will be described in this application note. basic circuit implementation of the proposed technique is also introduced. from a main input, denominated clock, generically swinging from a low to a high value, in two different time intervals, one or two square wave outputs, swinging from low to high in phase or in opposite with respect to the clock signal are generated. the digital control method is able to generate an output signals timing, so to anticipate output transitions from high to low levels with respect to the clock signal transitions. this technique makes it possible to realize a smart driver ic family (stsrx) for isolated smps topologies with the pwm controller located on the primary side. these ics, deriving the clock signal from the secondary output of the isolation transformer, are able to provide the proper gate drive signals to drive one or two synchronous rectifier mosfets gates, solving all the known problems in controlling synchronous rectification. 2. introduction. in the power conversion area, in low dc output voltage converters, the utilization of mosfets as rectifiers is a technique increasingly used for the beneficial effects on efficiency due to the reduced conduction losses on these devices. the way the synchronous rectifiers (srs) are controlled is fundamental for the correct operation of the circuit. proper techniques must be used to drive the srs according to the law of the diode that the sr is meant to replace. this driving signal has to be derived from the main pwm control signal, which determines the different states of the switch mode circuit and therefore the operating conditions for the diodes of the circuit. the way the driving signal is derived from the main pwm signal to properly control srs depends on the kind of topology used, and the presence of galvanic isolation in it. in a non-isolated smps topology, the synchronous rectifiers control circuit can get the information about the switching transitions (turn-off and turn-on of the main switch) from the main control circuit in a very simple way. in isolated topologies, with primary side control, the absence of pwm controlling signal in the secondary side of the isolation barrier makes the generation of the proper srs control signals even more difficult. if the equivalent diode law is not respected cross conduction or shoot-through between switches will july 2000 1/20 AN1288 application note stsrx family: mixed-signal ics to drive synchronous rectifiers in isolated smpss f. librizzi - p. scalia ?
AN1288 - application note 2/20 occur. this will be described in detail in the following. in all of these circumstances one of the switches is forced to conduct in the first quadrant, opposite its useful sense of conduction as a diode. therefore, switching losses can become predominant, spoiling most of the benefits introduced by the reduction of conduction losses on the rectifiers, or even bringing to destructive operations. the required timing of the driving signal for the synchronous rectifier is showed in figure 1, according to a general switch mode topology configuration with one switch and only one diode, where the conduction times possible for switch and diode are complementary. figure 1: synchronous rectification concept the dead time intervals carry out the function of preventing contemporary conduction (cross-conduction) of the main switch and the sr, but they must be reduced to the lowest possible value to minimize sr parasitic diode conduction times and consequent lost of efficiency. the switching losses caused by the reverse recovery current of the body-diode will be dependent of the carried current in the instant in which the voltage between anode and cathode reverses become negative. 3. synchronous rectification in isolated topologies. in isolated topologies, if the main pwm controller is located on the secondary side, the task of driving synchronous rectifiers can be easily solved. in fact, having pwm signals available on the secondary side it can be used to generate the driving signal for the srs by adding proper delays to each transition to compensate the propagation delays which are suffered by the driving signal transferred to the primary side through a coupling device. however, the secondary side control configuration shows several system disadvantages such as requirement of an auxiliary power supply for start-up of the converter, requirement of a crossing-isolation circuit able to transfer the pwm control driving signal to the primary switches and difficulties to transfer the information about the primary switch current to the pwm controller in current mode control loops. i ak v ka v gs, sr pwm signal i d v ds t t t d t2 d t2 d t1 d t1 v g v g k ad s g
AN1288 - application note 3/20 therefore, the use of pwm control on the primary side is mandatory to realize smps with top performances in terms of high efficiency, small dimension and low cost. in isolated topologies, if the main pwm control circuit is on the primary side, its output signal cannot be available on the secondary side in a simple, effective and cheap way. this information can be however derived on the secondary side from the output of the isolation transformer. due to the parasitic elements of the circuit, the synchronizing signal withdrawn at the output of the isolation transformer is delayed with respect to the primary pwm signal and may present some oscillations especially in discontinuous conduction mode. therefore, the control technique meant to provide srs driving must be able to prevent eventual rising of wrong operative conditions derived by any timing effect on the synchronization of the signal available on the secondary (pwm synchronization signal) with respect to the primary pwm signal. using the output of the isolation transformer as the pwm synchronization signal, a very simple way to make mosfets operate as rectifiers in isolated topologies based on forward topology is the technique called aself-driven synchronous rectificationo. unfortunately, this technique has a very serious inconvenience. in fact, the driving signal is depends on the way in which the main transformer is demagnetized (magnetic reset). as a consequence, the time in which the body diodes of the free-wheeling mosfet is forced to conduct can be very large, due to the fact that the driving signal for the gate is missing. this fact damages the main benefits introduced by synchronous rectification, restricting the use of this method for driving srs only in combination with some particular, and proprietary magnetic reset techniques. figure 2: synchronous rectifier driving signals in addition, this technique is hard to implement when the primary input voltage varies (the common factors are 2:1) in difficulty to always provide a value of driving signal compatible with the gates ranges. t on t off clock out1 t =1/f ss out2 d t2 d t2 d t1 d t1
AN1288 - application note 4/20 therefore, in isolated topologies with primary side control, the most proper approach to drive synchronous rectifiers requires a control circuit able to handle the synchronization signal (clock) withdrawn from the output of the isolation transformer, and to solve any other problem regarding the timing of the driving signals for the two mosfets with respect to the clock input. in figure 2 the general clock signal is displayed at a fixed switching frequency with the primary on and off switch time intervals together with two complementary sr driving signals (out1 and out2). 4. cross-conduction and shoot-through problems. the control circuit, necessary to use synchronous rectifiers in isolated topologies in simple ways, has to deal with proper timing generation of the sr driving signal from the clock signal input. according to figure 2, as already explained, proper deadtimes between clock signal and sr driving signal must be provided to avoid cross conduction between devices. another well-known phenomenon to be dealt with by the controller is the so called ashoot through problemo that may happen on the secondary side of an isolated topology. the specific mechanism of this wrong operation condition is dependent on the circuit topology, and it will be dealt with in detail in the following. in general, while the transition in which a synchronous rectifier has to be turned on reveals to be easy to deal with, the turn-off transition requires a special treatment. in fact, the circuitry that generates the driving signal from the clock introduces a propagation delay which is added to the one coming from the isolation transformer. in generating the sr transition, this intrinsic delay creates the dead time necessary to avoid wrong circuit conditions. this delay has to be minimized, because it causes body diode conduction, bringing penalties in terms of loss of efficiency. if the turn-off transitions for out1 and out2 (seen in figure 2) are not properly handled the circuit will show a very critical behavior. in fact, in this case, the intrinsic delay generates late turn-off of the bi-directional synchronous rectifiers switches creating wrong circuit conditions made normally impossible for the presence of the unidirectional diodes. the general condition can be defined as the creation of short circuit loops which can generate very high current peaks, limited only by the parasitic elements in the circuit. the particular analysis of this phenomenon will be described in details for each of the main isolated topology family. therefore, the introduction of a special deadtime is necessary in order to be able to avoid the generation of the wrong operation conditions. this can be realized by generating a proper anticipation of the turn-off transition that is able to guarantee that the sr can be off before the clock signal transition. this anticipation, however, as in the turn-on transition, has to be minimized to reduce the body-diode conduction time in order to avoid penalties on the efficiency. in particular, the amount of anticipation can be used as on optimization parameter to adjust the operation of the circuit to its physical implementation by design. in fact, the time slope of the decreasing current on the sr which has been turned off is dependent by several parameters, such as input and output voltage of the converter, the amount of previously driven current and, above all, by the parasitic elements in the circuit like the leakage inductance. the anticipation time can be adapted to the specific operation condition of the circuit to achieve the best performance in terms of efficiency, setting to minimum the conduction times of the body-diodes and the consequent reverse recovery currents.
AN1288 - application note 5/20 in figure 2 the required anticipation intervals, denominated by d t1 and d t2, are introduced in the most general case of two complementary sr driving signals generated from a clock input. the mechanism of generation of the shoot-through will now be examined for the main isolated topologies of smps converters. 4a. single ended forward topology now we will examine the operations in a single ended forward topology circuit pointing out in particular the eventual generation of the shoot-through, displayed in figure 3. figure 3: control driven synchronous rectification in forward topology the synchronous rectifiers control circuit, achieving the clock information from the voltage on the node (8), generates the mosfet driving signals for the forward rectifier (fr) and for free-wheeling (fw). the voltage formation on node (8) shows some delay with respect to the primary mosfet (4) driving signal, mainly coming from the isolation transformer (5) parasitic. this delay, added to the propagation delay of the srs controller, causes a delayed turn-off of the sr(1) or of the sr(2), and as a consequence shoot-through on the secondary output of the isolation transformer loop occurs in both transitions in which the mosfet (4) is turned on or off. vin pwm controller synchronous rectifiers controller out1 out2 clock isolatio n 1 2 3 4 5 6 7 8
AN1288 - application note 6/20 figure 4: shoot-through condition referring to figure 3, when the primary mosfet (4) is turned-on, the voltage on node (8) tends to go positive. this voltage forward biases the body diode of the fr (2) and, due to the delay in turning-off the fw (1), an unlimited current can flow in the short circuit loop determined by the fw (1), the body-diode of the fr(2) and the secondary winding of the isolation transformer. the value of the short circuit current is only limited by the parasitic of the circuit and eventually by the primary side protection circuits included in the pwm (figure 4). in the other transition, when the mosfet (4) is turned-off, the voltage on node (8) becomes negative. if the sr (2) is still on due to the delay of the clock input information, this negative voltage forward biases the body-diode of the sr (1), and a short circuit loop is formed by the body-diode of the sr (1), the sr (2) (still on) and the secondary winding of the isolation transformer (5). in order to avoid this bad condition, an anticipation in turning off the fw and the fr mosfets is needed. the detailed timing for a correct operation of the circuit, according to the concept of anticipation is shown in figure 5. in both of the two sr turn-off transistions for the free-wheeling fw (1) (fw) and the fr (2) (fr), the time interval t 0 -t 1 is the amount of anticipation, while t 0 -t 3 is the entire dead time between the two complementary driving signals. in the interval t 0 -t 2 the body-diode conducts, reversing after t 2 . 4 3 4 3 v gs, fw primary mosfet on t t t t 0 t 1 primary mosfet on magnetic reset t t t t 0 t 1 v s i fr v s fw fr v out v s fw fr v out
AN1288 - application note 7/20 figure 5: fw turn-off transition and anticipation time in forward topology 4b. flyback topology we will now examine the operations in a flyback topology circuit, displayed in figure 6. most of the considerations made for the forward topology are still valid, but, in this case, the topology shows only one mosfet working as a rectifier. the sr(1) has to be turned-on when the main primary switch (4) is off and viceversa. when the mosfet (4) is turned on the voltage at the output of the isolation transformer, referenced to node (2), goes from vo to -vin, and if the sr(1) is not already off, a short circuit loop is generated with the output capacitor (3) put in parallel to a negative voltage that tries to impulsively discharge the capacitor with an unlimited current. this causes an unavoidable serious drop in the regulated output voltage. even in this case, an anticipation in turning-off the sr solves the problem. (figure 7) figure 6: control driven synchronous rectification in flyback topology primary mosfet on primary mosfet on clock v gs, fw i fw i fr v ds fr v ds fw clock i fw i fr v ds fr v ds fw v gs, fr transformer reset already completed different magnetic reset technique t o t 1 t 2 t 3 t o t 1 t 2 t 3 t t t t t t t t t t t t synchronous rectifiers controller pwm controller v in out clock isolatio n 1 2 3 4 5 6 8 v o
AN1288 - application note 8/20 synchronous rectifiers controller isolation pwm controller v in clock 1 clock 2 out 1 out 2 v o push-pull half-bridge full-bridge 1 2 3 4 5 6 7 8 9 10 11 figure 7: sr. turn-off transition and anticipation time in flyback topology figure 8: control driven synchronous rectification in double-ended topologies 4c. double-ended topologies similar consideration are valid for all the forward derived double ended isolated topologies (push-pull, half bridge, full bridge), displayed in figure 8. the synchronization clock input withdrawn at node (3) is used by the sr control circuit to generate the proper timing signal for the sr(2). in a similar way, the synchronization clock input withdrawn at node (4) is used to generate the proper timing signal for the fs=1/ts clock out d t d t t t t t t t clock v gs sr i sr v ds sr primary mosfet on t-t= t 10 d t 0 t 1 t 2
AN1288 - application note 9/20 sr(1). in both cases the synchronization clock and the relative output driving signal are displayed in figure 9. in this case, the anticipation times in turning-off the mosfets are necessary to avoid short circuit loops formed in both transitions by the two srs (one sr and one body-diode) and the secondary winding of the isolation transformer, with a worsening of the converter efficiency. the detailed timing of the srs turn-off transitions (two identical) relative to the forward double-ended topologies circuit is showed in figure 9. figure 9: synchronous rectifiers turn-off transition and anticipation time in double ended topologies 5. description of the digital method to generate the srs driving signals. the proposed method is meant to generate the proper driving signals for synchronous rectifiers from a clock signal input, related to the main pwm signal of the switch-mode circuit. in particular, it is able to operate according to the timing displayed in figure 2, realizing proper anticipation times in correspondence of the turning-off transitions of the outputs. these functions are implemented through the basic concept of synchronizing the operation of the control circuit to the clock signal at the converter switching frequency, and, in particular, to its transitions. this is realized by means of an oscillator at a frequency much higher than the switching frequency of the primary dead time primary dead time primary dead time primary dead time fs=1/ts fs=1/ts d t1 d t1 d t2 d t2 clock 1 clock 2 out 1 out 2 clock 1 v gs sr 1 i sr 1 v ds sr 1 clock 2 v gs sr 2 i sr 2 v ds sr 2 t 0 t 1 t 2 t 0 t 1 t 2 t t t t t t t t t t t t t-t= t1 10 d t-t= t2 10 d
AN1288 - application note 10/20 fsm finite states machine counters up/down out1 counters up/down out2 osc internal clock up/down output counter t on t s control out1 control out2 clock input set anticipation 1 set anticipation 2 out1 out2 converter (f s ) and of two digital counters blocks which play different roles: one operates the measure of the entire switching period, cycle-by-cycle, storing this information for the next cycle. the other one makes the same revelation for the on or off time of the clock signal, according to the specific need of the circuit topology. the precision and resolution of the system is related to the internal digital frequency of operation, used to implement this method. being available the period and on/off time intervals parameters of the previous cycle, a proper timing of the outputs can be easily generated in the following cycle, and in particular a proper anticipation on the turning-off transitions can be set. the amount of the anticipation can be set accordingly with the resolution of the system, in terms of discrete quantities of minimum digital pulse period. timing of the proposed control technique will be shown in the following, together with the detailed explanation of the control method operation, according to the description of the apparatus through which it is implemented. in the more general case of two complementary signals on the secondary side, the general structure of the system is composed by an internal oscillator, a finite states machine, two couple of up/down counters, two control output logic blocks (figure 10). this system structure has three inputs and two outputs: the outputs are the driving signals for the two mosfets on the secondary side of the converter; the inputs are the clock (ck), the anticipation time setting for the out1 and the anticipation time setting for the out2. figure 10: general structure of the system the finite states machine , synchronized with the rising edges of the internal oscillator clock signal (cki) at frequency fi>fs (period ti ), is the brain of the system and generates the two signals out1 and out2
AN1288 - application note 11/20 without any overlap in turn-on and turn-off conditions. a square wave signal of frequency fs (period ts ), said switching frequency is present at the clock input; the anticipation times are externally set through the relative inputs. the two counters work in a different way, down to anticipate the turn-off of the outputs and up in order to continuously get the information about the duration of the switching period for the out2 or the duration of the ton time for the out1. in this way, the output anticipation in a switching period in turn-off is based on the information stored in the previous switching period. a continuous monitoring of the switching period and of the ton time is obtained cycle by cycle. the bit number of the counters relative to the out2 are chosen according to the minimum and the maximum operating switching frequency of the converter. the bit numbers of the counters relative to the out1 are chosen according to the minimum and the maximum ton of the converter. 5a. steady conditions in steady state conditions (fixed switching frequency and fixed duty-cycle), for the two following switching period, the part of the system relative to the out2 operates as follow (figure 11): - first switching period: on the rising edge of the clock input, the first of the two up/down counters starts to count up the pulses of the internal clock (cki). on the next rising edge of the clock input (end of the first period ts ) the counter stops its calculation. the number of pulses counted ( n2 ) takes account of the duration of the switching period. this information is stored in order to be used in the next switching period. - second switching period: on the rising edge of the ck input, the first counter counts down the pulses of the internal clock stopping its calculation to n2-x2 , at this time the out2 is turned off. the second counter, counting the new number of pulses of the internal clock, updates the information about the duration of the switching period ts . the amount of anticipation in turning-off the out2 is given by x2ti , and is set by the out2 anticipation time input. in each period the function of the counters, up or down, is exchanged with respect to the previous period.
AN1288 - application note 12/20 figure 11: out2 anticipation time generation for the part of the system relative to the out1 the other two up/down counters take in account the information about the duration of the ton time in order to anticipate the turn-off of the out1 (figure 12): - first switching period: the first counter starts to count on the rising edge of the clock input and stops its calculation on the falling edge. the number of pulses counted are n1 and this information takes in account of the ton time. figure 12: out1 anticipation time generation t time on t time on clock input internal clock out1 n pulses 1 n-x pulses 11 x pulses 1 anticipation previous period anticipation x *t1 1 1st switching per iod ts 2nd switching period ts clock input internal clock out2 n pulses 2 n -x pulses 22 x pulses 2 anticipation previous period anticipation x *t1 2
AN1288 - application note 13/20 - second switching period: the first counter counts down stopping its calculation to n1-x1 giving an anticipation in turning-off the out1 equal to x1 ti , this anticipation is set through the out1 anticipation time input. the second counter counts upward the number of pulses of the internal clock between the rising edge and the falling edge of the clock input during the current period. 5b. varying conditions for the out2, when a variation in the switching frequency occurs, three different cases are possible: 1. the switching period in which the anticipation is realized is smaller than the previous period (figure 13). in this case the turning-off of the out2 would be delayed and not anticipated with respect to the clock input. this condition is avoided forcing, in any case, the turn-off of the out2 with the rising edge of the clock input. 2. the switching period in which the anticipation is realized is larger than the previous period (figure 14). in this case an early turn-off of the out2 happens. the conduction time of the body-diode of the mosfet is not minimized just for one cycle and the loss of efficiency is very low. figure 13: switching frequency variation: ts1 > ts2 3. the switching period in which the anticipation is realized has a ton time equal or larger than the previous period (figure 15). in this case the out2 is kept off. even in this case the conduction time of the body-diode of the mosfet is not minimized for only one cycle causing a very low loss of efficiency. 1st switching period t s1 2nd switching period t s2 clock input internal clock out2 n pulses 2 n -x pulses 22 anticipation previous period forced turn-off (no anticipation) expected turn-off t>t s1 s2
AN1288 - application note 14/20 1st switching period t s1 2nd switching period t time on t AN1288 - application note 15/20 figure 16: duty-cycle variation: ton1 > ton2 2. the ton time in which the anticipation is realized is larger than the previous ton time (figure 17). in this case an early turn-off of the out1 happens. the conduction time of the body-diode of the mosfet is not minimized just for one cycle and the loss of efficiency is very low. figure 17: duty-cycle variation: ton1 < ton2 t on1 t on2 tt on1 on2
AN1288 - application note 16/20 the described method implements a cycle-by-cycle control because the measurement taken in a period determines the action in the next period. by setting the value of x1 ( x2 ) the amount of anticipation in turning-off the synchronous rectifier mosfet is chosen among different discrete values. the time step is ti , so the higher the internal oscillator frequency fi is the more accurate the anticipation time is. 6. implementation of the control method in the stsrx family the method of controlling the turn-off time of synchronous rectifiers is implemented in a silicon device family: 6a. stsr2 the stsr2 is the device designed to drive two synchronous rectifiers in single ended forward topology applications. the ic includes the described control system, two high-current n-channel mosfet drivers and a clock buffer circuit needed to adapt the clock signal to the accepted values, with the following pin output (figure 18): figure 18. stsr2 in forward converter vcc: the supply input is from 4.5v to 5.5v which allows applications with logic mosfets. the uvlo feature proper start-up is guaranteed while it avoids undesirable driving during eventual dropping of the supply voltage. pwrgnd: reference for power signals. this pin carries the full peak currents from the outputs. sglgnd: reference for all the control logic signals. this pin is completely separate from the pwrgnd to prevent eventual disturbances that could affect the control logic. ck: this input provides synchronization for ic operations, being the transitions between the two output conditions based on a positive threshold, equal for the two slopes. the smart clock revelation mechanism makes these operations independent by false triggering pulses generated in light load conditions and by particular demagnetization techniques. outgate1,2: the two high current outputs are complementary without any overlap between the pwm v in sr1 sr2 v out pre-reg r1 r2 r3 r3 out gate2 out gate1 v cc set ant2 inhibit clock sglgnd pwmgnd stsr2
AN1288 - application note 17/20 on-times due to the self generation of dead times of the ic. setant2: sets the anticipation in turning-off the outgate2. it is possible to choose among four different anticipation times by discrete partitioning of the supply voltage inhibit: this input enables outgate2 when kept to a negative value larger than the very low threshold voltage. otherwise it forces the outgate2 to a minimum conduction time. in typical forward converter applications it is possible to turn off the freewheeling synchronous rectifier when the current through it tends to reverse. this allows discontinuous conduction modes and providing protection to the converter from eventual sinking current from the load. 6b. stsr3 the stsr3 is the device designed to drive one synchronous rectifier in flyback topology applications. the ic includes the described control system, with the same logic operation, but only for the art relative to out2, one high-current n-channel mosfet driver and a clock buffer circuit needed to dapt the clock signal to the accepted values. the pin output is the same of the stsr2 one, but with only one outgate (figure 19). figure 19: stsr3 in flyback converter 6c. stsr4 the stsr4 is the device designed to drive two synchronous rectifiers in double-ended topology applications (push pull, half bridge, full bridge). the device includes a dual structure based on the duplication of the described control systems for the part relative to out2, two high-current n-channel mosfet drivers and two clock buffer circuits are needed to adapt the clock signal to the accepted values. the function of the pins is the same of stsr2 and the application circuit is displayed in figure 20. pwm v in v out v aux r3 r3 r1 r2 d 1 c 1 inhibit out gate pwrgnd sglgnd clock set ant v cc stsr3
AN1288 - application note 18/20 v in push-pull half-bridge full-bridge pwm v out r3 r3 r1 r2 pre-reg out gate2 out gate1 clock1 clock2 sglgnd pwrgnd set ant v cc stsr4 figure 20: stsr4 in generic double-ended converter 7. conclusion the technique here disclosed is meant to realize a control-driven approach for synchronous rectification in smps isolated topologies. the control-driven technique presents several advantages with respect to the self-driven approach. it realizes independence from the isolation transformer reset technique, being the conduction time of the body-diode of the minimized mosfets, while the driving signal values can always be made compatible with the gates ranges. using some additional particular techniques, it is also possible to allow the discontinuous conduction mode operation of the converter. the technique allows the convenience to use the pwm controller on the primary side of the isolated topology, deriving synchronization information directly from the secondary side. the method solves any of the known operation problems regarding the generation of synchronous rectifiers driving signals, like cross-conduction and shoot-through, while it allows the minimization of the body-diode conduction. with respect to other techniques, which implement the same control driven approach, and also able to solve all the mentioned problems, the proposed method and the related implementing apparatus show several advantages and benefits. in particular the proposed digital technique allows the implementation of a very simple circuit configuration required by the stsrx device to operate correctly when inserted in a smps topology circuit. the ic can be realized with a very minimal pin count. no particular accuracy or stability in time and temperature is required for the eventual external components, resistors, to be used to set the anticipation times.
AN1288 - application note 19/20 in addition the method shows excellent characteristics in term of fast response to transients coming from the converter switching frequency and sudden duty-cycle variations. all the other techniques, based on the analog approach to realize the turn-off transitions anticipation function, show weakness due to the need of several external components, mainly capacitors with very tight tolerance and stability. these are needed to allow the correct operation of the relative technique and apparatus. other techniques based on the pll approach to realize the turn-off transitions anticipation function require a huge number of external components, with relative high pin count in the synthesizing device, to set all the parameters that are necessary to the proper operation of the control method, by means of complex design relations. in addition they show very slow response to transients, due to switching frequency and duty-cycle perturbations, which reflects negatively on the overall efficiency of the converter. the described method is fast because the control is made cycle-by-cycle. therefore it acts suddenly on the next cycle after a disturbance of the steady state occurs. in addition, due to the high flexibility of the digital approach, eventual correctional algorithms can be easily implemented in the switching frequency synchronization, generating error-correction procedures and similar improvements of the presented approach. due to the digital nature of the method, the anticipation time can be set only by discrete steps. however, by increasing the digital oscillator frequency the time step can be reduced and a more precise resolution can be achieved with a more flexible determination of switching timing. references 1. franco lentini, fabrizio librizzi, pietro scalia, ignazio cal method and apparatus to digitally control turn-off time of synchronous rectifiers in isolated topologies for switched mode power supplies european patent pending #00830274.7. 2. stsr2 target specification 3. stsr3 target specification 4. d. jitaru - ahigh efficiency dc/dc convertero - hfpc proceedings, april 1994 5. m. m. jovanovic, m. t. zhang, f. c. lee - aevaluation of synchronous-rectification efficiency improvement limits in forward convertero - ieee transaction on industrial electronics, vol. 42, no.4, august 1995 6. h. p. yee, s. sawahata - aa balanced review of synchronous rectifiers in dc/dc converterso - pesc 1999
AN1288 - application note 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://ww w.st.com

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